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LT1711/LT1712 Single/Dual 4.5ns, 3V/5V/5V, Rail-to-Rail Comparators
FEATURES
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DESCRIPTIO
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Ultrafast: 4.5ns at 20mV Overdrive 5.5ns at 5mV Overdrive Rail-to-Rail Inputs Rail-to-Rail Complementary Outputs (TTL/CMOS Compatible) Specified at 2.7V, 5V and 5V Supplies Output Latch Inputs Can Exceed Supplies Without Phase Reversal LT1711: 8-Lead MSOP Package LT1712: 16-Lead Narrow SSOP Package
The LT(R)1711/LT1712 are UltraFastTM 4.5ns comparators featuring rail-to-rail inputs, rail-to-rail complementary outputs and an output latch. Optimized for 3V and 5V power supplies, they operate over a single supply voltage range from 2.4V to 12V or from 2.4V to 6V dual supplies. The LT1711/LT1712 are designed for ease of use in a variety of systems. In addition to wide supply voltage flexibility, rail-to-rail input common mode range extends 100mV beyond both supply rails, and the outputs are protected against phase reversal for inputs extending further beyond the rails. Also, the rail-to-rail inputs may be taken to opposite rails with no significant increase in input current. The rail-to-rail matched complementary outputs interface directly to TTL or CMOS logic and can sink 10mA to within 0.5V of GND or source 10mA to within 0.7V of V +. The LT1711/LT1712 have internal TTL/CMOS compatible latches for retaining data at the outputs. Each latch holds data as long as the latch pin is held high. Latch pin hysteresis provides protection against slow moving or noisy latch signals. The LT1711 is available in the 8-pin MSOP package. The LT1712 is available in the 16-pin narrow SSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation. UltraFast is a trademark of Linear Technology Corporation.
APPLICATIO S
s s s s s s s s s s s
High Speed Automatic Test Equipment Current Sense for Switching Regulators Crystal Oscillator Circuits High Speed Sampling Circuits High Speed A/D Converters Pulse Width Modulators Window Comparators Extended Range V/F Converters Fast Pulse Height/Width Discriminators Line Receivers High Speed Triggers
TYPICAL APPLICATIO
A 4x NTSC Subcarrier Voltage-Tunable Crystal Oscillator
5V 1N4148 1M 5V 1M 2k 100pF MV-209 VARACTOR DIODE 1M* 47k* LT1004-2.5 3.9k* 1k*
5.5
LT1711/LT1712 Propagation Delay vs Input Overdrive
VIN 0V TO 5V
6.0 TA = 25C V+ = 5V V - = 0V VSTEP = 100mV tPD+
1M
0.047F C SELECT (CHOOSE FOR CORRECT PLL LOOP RESPONSE)
PROPAGATION DELAY (ns)
5.0 4.5 4.0 3.5 3.0 0 10
390
+
LT1711
Y1** 15pF 100pF
-
2k 200pF
FREQUENCY OUTPUT
171112 TA01
* 1% FILM RESISTOR ** NORTHERN ENGINEERING LABS C-2350N-14.31818MHz
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tPD- 20 40 50 30 INPUT OVERDRIVE (mV) 60
171112 TA02
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LT1711/LT1712
ABSOLUTE AXI U RATI GS
Supply Voltage V + to V - ............................................................ 12.6V V + to GND ........................................................ 12.6V V - to GND .............................................- 10V to 0.3V Differential Input Voltage ................................... 12.6V Latch Pin Voltage ...................................................... 7V Input and Latch Current ..................................... 10mA
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
TOP VIEW V+ +IN -IN V- 1 2 3 4 8 7 6 5 Q Q GND LATCH ENABLE
LT1711CMS8 LT1711IMS8 MS8 PART MARKING LTTC LTTD
MS8 PACKAGE 8-LEAD PLASTIC MSOP
TJMAX = 150C, JA = 250C/ W (NOTE 12)
Consult factory for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V + = 2.7V or V + = 5V, V - = 0V, VCM = V +/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER V+ VOS Positive Supply Voltage Range Input Offset Voltage (Note 4) RS = 50, VCM = V +/2 RS = 50, VCM = V +/2 RS = 50, VCM = 0V RS = 50, VCM = V + CONDITIONS
q q
VOS/T IOS IB VCM CMRR
Input Offset Voltage Drift Input Offset Current
Input Bias Current (Note 5)
q
Input Voltage Range (Note 9) Common Mode Rejection Ratio V + = 5V, 0V VCM 5V V + = 5V, 0V VCM 5V V + = 2.7V, 0V VCM 2.7V V + = 2.7V, 0V VCM 2.7V 2.4V V + 7V, VCM = 0V
PSRR+
Positive Power Supply Rejection Ratio
2
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(Note 1)
Output Current (Continuous) .............................. 20mA Operating Temperature Range ................ - 40C to 85C Specified Temperature Range (Note 2) ... - 40C to 85C Junction Temperature .......................................... 150C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
TOP VIEW -IN A +IN A V- V
+
1 2 3 4 5 6 7 8
LATCH ENABLE A 15 GND 16 14 Q A 13 Q A 12 Q B 11 Q B 10 GND LATCH 9 ENABLE B
ORDER PART NUMBER LT1712CGN LT1712IGN GN PART MARKING 1712 1712I
V+ V
-
+IN B -IN B
GN PACKAGE 16-LEAD PLASTIC SSOP
TJMAX = 150C, JA = 120C/ W (NOTE 12)
MIN 2.4
TYP 0.5 0.7 1
MAX 7 5.0 6.0
UNITS V mV mV mV mV V/C A A A A V dB dB dB dB dB dB
q q
10 0.2 - 18 - 35 - 0.1 56 53 54 50 58 56 65 65 75 -5 3 6 5 10 V + + 0.1
q q q q
LT1711/LT1712
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V + = 2.7V or V + = 5V, V - = 0V, VCM = V +/2, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER PSRR- AV VOH VOL I+ I- VIH VIL IIL tPD tPD tr tf tLPD tSU tH tDPW fMAX tJITTER Negative Power Supply Rejection Ratio Small-Signal Voltage Gain (Note 10) Output Voltage Swing HIGH Output Voltage Swing LOW Positive Supply Current (Per Comparator) Negative Supply Current (Per Comparator) Latch Pin High Input Voltage Latch Pin Low Input Voltage Latch Pin Current Propagation Delay (Note 6) VLATCH = V + VIN = 100mV, VOVERDRIVE = 20mV VIN = 100mV, VOVERDRIVE = 20mV VIN = 100mV, VOVERDRIVE = 5mV VIN = 100mV, VOVERDRIVE = 20mV 10% to 90% 90% to 10% IOUT = 1mA, VOVERDRIVE = 50mV IOUT = 10mA, VOVERDRIVE = 50mV IOUT = - 1mA, VOVERDRIVE = 50mV IOUT = - 10mA, VOVERDRIVE = 50mV V + = 5V, VOVERDRIVE = 1V
q q q q q
CONDITIONS - 7V V - 0V, V + = 5V, V
CM = 5V
MIN
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TYP 80 15 V+ - 0.2 V+ - 0.4 0.20 0.35 15 8
MAX
UNITS dB dB V/mV V V
60 58 1 V+ - 0.5 V+ - 0.7
0.4 0.5 19 26 10 13 0.8 15
V V mA mA mA mA V V A ns ns ns ns ns ns ns ns ns ns MHz psRMS
V + = 5V, VOVERDRIVE = 1V
q q q q
2.4
4.5
q
6.0 8.5 1.5
5.5 0.5 2 2 5 1 0 5
Differential Propagation Delay (Note 6) Output Rise Time Output Fall Time Latch Propagation Delay (Note 7) Latch Setup Time (Note 7) Latch Hold Time (Note 7) Minimum Latch Disable Pulse Width (Note 7) Maximum Toggle Frequency Output Timing Jitter
VIN = 100mVP-P Sine Wave VIN = 630mVP-P (0dBm) Sine Wave, f = 30MHz
100 11
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V + = 5V, V - = - 5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER V+ V- VOS Positive Supply Voltage Range Negative Supply Voltage Range (Note 3) Input Offset Voltage (Note 4) RS = 50, VCM = 0V RS = 50, VCM = 0V RS = 50, VCM = 5V RS = 50, VCM = -5V CONDITIONS
q q q
MIN 2.4 -7
TYP
MAX 7 0
UNITS V V mV mV mV mV V/C A A A A V dB dB dB dB dB dB
0.5 0.7 1 10 0.2
q
5.0 6.0
VOS/T IOS IB VCM CMRR PSRR+ PSRR-
Input Offset Voltage Drift Input Offset Current Input Bias Current (Note 5)
q
3 6 5 10 5.1
- 18 - 35 - 5.1 61 58 58 56 60 58
-5
Input Voltage Range Common Mode Rejection Ratio Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio - 5V VCM 5V
q q
75 85 80
2.4V V + 7V, VCM = - 5V
q
- 7V V - 0V, VCM = 5V
q
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LT1711/LT1712
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V + = 5V, V - = - 5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified.
SYMBOL PARAMETER AV VOH VOL I+ I- VIH VIL IIL tPD tPD tr tf tLPD tSU tH tDPW fMAX tJITTER Small-Signal Voltage Gain Output Voltage Swing HIGH (Note 8) Output Voltage Swing LOW (Note 8) Positive Supply Current (Per Comparator) Negative Supply Current (Per Comparator) Latch Pin High Input Voltage Latch Pin Low Input Voltage Latch Pin Current Propagation Delay (Notes 6, 11) VLATCH = V+ VIN = 100mV, VOVERDRIVE = 20mV VIN = 100mV, VOVERDRIVE = 20mV VIN = 100mV, VOVERDRIVE = 5mV VIN = 100mV, VOVERDRIVE = 20mV 10% to 90% 90% to 10% IOUT = 1mA, VOVERDRIVE = 50mV IOUT = 10mA, VOVERDRIVE = 50mV IOUT = - 1mA, VOVERDRIVE = 50mV IOUT = - 10mA, VOVERDRIVE = 50mV VOVERDRIVE = 1V
q q q q q
CONDITIONS
MIN 1 4.5 4.3
TYP 15 4.8 4.6 0.20 0.30 17 9
MAX
UNITS V/mV V V
0.4 0.5 22 30 12 15 0.8 15
V V mA mA mA mA V V A ns ns ns ns ns ns ns ns ns ns MHz psRMS
VOVERDRIVE = 1V
q q q q
2.4
4.5
q
6.0 8.5 1.5
5.5 0.5 2 2 5 1 0 5
Differential Propagation Delay (Notes 6, 11) Output Rise Time Output Fall Time Latch Propagation Delay (Note 7) Latch Setup Time (Note 7) Latch Hold Time (Note 7) Minimum Latch Disable Pulse Width (Note 7) Maximum Toggle Frequency Output Timing Jitter
VIN = 100mVP-P Sine Wave VIN = 630mVP-P (0dBm) Sine Wave, f = 30MHz
100 11
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1711C/LT1712C are guaranteed to meet specified performance from 0C to 70C. They are designed, characterized and expected to meet specified performance from - 40C to 85C but are not tested or QA sampled at these temperatures. The LT1711I/LT1712I are guaranteed to meet specified performance from -40C to 85C. Note 3: The negative supply should not be greater than the ground pin voltage and the maximum voltage across the positive and negative supplies should not be greater than 12V. Note 4: Input offset voltage (VOS) is measured with the LT1711/LT1712 in a configuration that adds external hysteresis. It is defined as the average of the two hysteresis trip points. Note 5: Input bias current (IB) is defined as the average of the two input currents. Note 6: Propagation delay (tPD) is measured with the overdrive added to the actual VOS. Differential propagation delay is defined as: tPD = tPD+ - tPD-. Load capacitance is 10pF. Due to test system requirements, the LT1711/LT1712 propagation delay is specified with a 1k load to ground for 5V supplies, or to mid-supply for 2.7V or 5V single supplies. Note 7: Latch propagation delay (tLPD) is the delay time for the output to respond when the latch pin is deasserted. Latch setup time (tSU) is the
interval in which the input signal must remain stable prior to asserting the latch signal. Latch hold time (tH) is the interval after the latch is asserted in which the input signal must remain stable. Latch disable pulse width (tDPW) is the width of the negative pulse on the latch enable pin that latches in new data on the data inputs. Note 8: Output voltage swings are characterized and tested at V + = 5V and V - = 0V. They are guaranteed by design and correlation to meet these specifications at V - = - 5V. Note 9: The input voltage range is tested under the more demanding conditions of V + = 5V and V - = -5V. The LT1711/LT1712 are guaranteed by design and correlation to meet these specifications at V - = 0V. Note 10: The LT1711/LT1712 voltage gain is tested at V+ = 5V and V - = -5V only. Voltage gain at single supply V+ = 5V and V+ = 2.7V is guaranteed by design and correlation. Note 11: The LT1711/LT1712 tPD is tested at V + = 5V and 2.7V with V - = 0V. Propagation delay at V + = 5V, V - = -5V is guaranteed by design and correlation. Note 12: Care must be taken to make sure that the LT1711/LT1712 do not exceed TJMAX when operating with 5V supplies over the industrial temperature range. TJMAX is not exceeded for DC inputs, but supply current increases with switching frequency (see Typical Performance Characteristics).
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LT1711/LT1712 TYPICAL PERFOR A CE CHARACTERISTICS
Input Offset Voltage vs Temperature
2.5 2.0
INPUT OFFSET VOLTAGE (mV)
V+ = 5V V - = 0V
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
1.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 - 2.5 -50 -25 50 0 75 25 TEMPERATURE (C) 100 125 VCM = 0V VCM = 5V VCM = 2.5V
6.0 5.5
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
5.0 4.5 4.0 3.5 3.0 -1
TA = 25C V+ = 5V V - = 0V VOD = 20mV VSTEP = 100mV CLOAD = 10pF
6.0 5.5 5.0 4.5
POSITIVE SUPPLY CURRENT (PER COMPARATOR) (mA)
Propagation Delay vs Input Common Mode Voltage
tPD+
tPD
-
0
3 4 5 2 INPUT COMMON MODE (V)
1
NEGATIVE SUPPLY CURRENT (PER COMPARATOR) (mA)
POSITIVE SUPPLY CURRENT (PER COMPARATOR) (mA)
Positive Supply Current vs Switching Frequency
40 TA = 25C V+ = 5V V - = 0V CLOAD = 10pF
30
10 8 6 4 2 0 0 -6 -3 -4 -5 -1 -2 NEGATIVE SUPPLY VOLTAGE (V) -7 I - AT -55C I - AT 25C I - AT 85C
INPUT BIAS CURRENT (A)
20
10
0
0
10 20 30 40 50 SWITCHING FREQUENCY (MHz)
UW
171112 G01
171112 G04
171112 G07
Propagation Delay vs Load Capacitance
10 9 8 7 6 5 4 3 0 20 80 60 100 40 LOAD CAPACITANCE (pF) 120 TA = 25C V+ = 5V V - = 0V VCM = 2.5V VOD = 20mV VSTEP = 100mV tPD- tPD+
Propagation Delay vs Temperature
8 7 6 5 4 3 2 1 V+ = 5V V - = 0V VCM = 2.5V VOD = 20mV VSTEP = 100mV CLOAD = 10pF 0 25 50 75 100 125 TEMPERATURE (C)
171112 G03
tPD-
tPD+
0 -50 -25
171112 G02
Propagation Delay vs Positive Supply Voltage
TA = 25C V - = 0V VCM = 2.5V VOD = 20mV VSTEP = 100mV CLOAD = 10pF
Positive Supply Current vs Positive Supply Voltage
25 V - = - 5V 20 V - = 0V
tPD+
15
tPD- 4.0 3.5 3.0
10
5 VIN = 100mV IOUT = 0mA 0 0
I+ AT -55C I+ AT 25C I+ AT 85C 12
6
0
6 8 4 POSITIVE SUPPLY VOLTAGE (V)
2
10
171112 G05
4 6 8 10 2 POSITIVE SUPPLY VOLTAGE (V)
171112 G06
Negative Supply Current vs Negative Supply Voltage
14 12 V += 5V VIN = 100mV IOUT = 0mA
10
Input Bias Current vs Input Common Mode Voltage
V + = 5V V - = 0V VIN = 0mV
4
-2
-8
-14
IB AT -55C IB AT 25C IB AT 125C -1 3 2 4 0 1 5 INPUT COMMON MODE VOLTAGE (V) 6
60
-20
171112 G08
171112 G09
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LT1711/LT1712 TYPICAL PERFOR A CE CHARACTERISTICS
Input Bias Current vs Temperature
0 -1 V+ = 5V V - = 0V VCM = 2.5V
INPUT BIAS CURRENT (A)
OUTPUT VOLTAGE (V)
4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 VOH AT -55C VOH AT 25C VOH AT 125C 0.1 1.0 10 SOURCE CURRENT (mA) 100
171112 G11
OUTPUT VOLTAGE (V)
-2 -3 -4 -5 -6 -7 -8 -50 -25 0 25 50 75 100 125
TEMPERATURE (C)
171112 G10
Output Timing Jitter vs Switching Frequency
100 90 TA = 25C V + = 5V V - = 0V VCM = 2.5V VIN = 630mVP-P (0dBm) SINE WAVE
OUTPUT TIMING JITTER (psRMS)
80 70 60 50 40 30 30 10 0 0 20
60 40 FREQUENCY (MHz)
PI FU CTIO S
LT1711 V + (Pins 1): Positive Supply Voltage, Usually 5V. + IN (Pin 2): Noninverting Input. - IN (Pin 3): Inverting Input. V - (Pins 4): Negative Supply Voltage, Usually 0V or - 5V. LATCH ENABLE (Pin 5): Latch Enable Input. With a logic high, the output is latched. GND (Pin 6): Ground Supply Voltage, Usually 0V. Q (Pin 7): Noninverting Output. Q (Pin 8): Inverting Output.
6
UW
80
171112 G13
Output High Voltage vs Source Current
5.0 4.9 4.8 V + = 5V V - = 0V VIN = 100mV 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
Output Low Voltage vs Sink Current
V + = 5V V - = 0V VIN = 100mV
VOL AT -55C VOL AT 25C VOL AT 125C 0.1 1.0 10 SINK CURRENT (mA) 100
171112 G12
Output Rising Edge, 5V Supply
VIN VIN
Output Falling Edge, 5V Supply
Q
Q
171112 G14
171112 G15
100
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LT1711/LT1712
PI FU CTIO S
LT1712 - IN A (Pin 1): Inverting Input of A Channel Comparator. + IN A (Pin 2): Noninverting Input of A Channel Comparator. V - (Pins 3, 6): Negative Supply Voltage, Usually - 5V. Pins 3 and 6 should be connected together externally. V + (Pins 4, 5): Positive Supply Voltage, Usually 5V. Pins 4 and 5 should be connected together externally. + IN B (Pin 7): Noninverting Input of B Channel Comparator. - IN B (Pin 8): Inverting Input of B Channel Comparator. LATCH ENABLE B (Pin 9): Latch Enable Input of B Channel Comparator. With a logic high, the B output is latched. GND (Pin 10): Ground Supply Voltage of B Channel Comparator, Usually 0V. Q B (Pin 11): Noninverting Output of B Channel Comparator. Q B (Pin 12): Inverting Output of B Channel Comparator. Q A (Pin 13): Inverting Output of A Channel Comparator. Q A (Pin 14): Noninverting Output of A Channel Comparator. GND (Pin 15): Ground Supply Voltage of A Channel Comparator, Usually 0V LATCH ENABLE A (Pin 16): Latch Enable Input of A Channel Comparator. With a logic high, the A output is latched.
APPLICATIO S I FOR ATIO
Common Mode Considerations
The LT1711/LT1712 are specified for a common mode range of - 5.1V to 5.1V on a 5V supply, or a common mode range of - 0.1V to 5.1V on a single 5V supply. A more general consideration is that the common mode range is from 100mV below the negative supply to 100mV above the positive supply, independent of the actual supply voltage. The criteria for common mode limit is that the output still responds correctly to a small differential input signal. When either input signal falls outside the common mode limit, the internal PN diode formed with the substrate can turn on resulting in significant current flow through the die. Schottky clamp diodes between the inputs and the supply rails speed up recovery from excessive overdrive conditions by preventing these substrate diodes from turning on. Input Bias Current Input bias current is measured with the outputs held at 2.5V with a 5V supply voltage. As with any rail-to-rail
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differential input stage, the LT1711/LT1712 bias current flows into or out of the device depending upon the common mode level. The input circuit consists of an NPN pair and a PNP pair. For inputs near the negative rail, the NPN pair is inactive, and the input bias current flows out of the device; for inputs near the positive rail, the PNP pair is inactive, and these currents flow into the device. For inputs far enough away from the supply rails, the input bias current will be some combination of the NPN and PNP bias currents. As the differential input voltage increases, the input current of each pair will increase for one of the inputs and decrease for the other input. Large differential input voltages result in different input currents as the input stage enters various regions of operation. To reduce the influence of these changing input currents on system operation, use a low source resistance. Latch Pin Dynamics The internal latches of the LT1711/LT1712 comparators retain the input data (output latched) when their respective latch pin goes high. The latch pin will float to a low state when disconnected, but it is better to ground the
7
LT1711/LT1712
APPLICATIO S I FOR ATIO
latch when a flow-through condition is desired. The latch pin is designed to be driven with either a TTL or CMOS output. It has built-in hysteresis of approximately 100mV, so that slow moving or noisy input signals do not impact latch performance. For the LT1712, if only one of the comparators is being used at a given time, it is best to latch the second comparator to avoid any possibility of interactions between the two comparators in the same package. High Speed Design Techniques The extremely fast speed of the LT1711/LT1712 necessitates careful attention to proper PC board layout and circuit design in order to prevent oscillations, as with most high speed comparators. The most common problem involves power supply bypassing which is necessary to maintain low supply impedance. Resistance and inductance in supply wires and PC traces can quickly build up to unacceptable levels, thereby allowing the supply voltages to move as the supply current changes. This movement of the supply voltages will often result in improper operation. In addition, adjacent devices connected through an unbypassed supply can interact with each other through the finite supply impedances. Bypass capacitors furnish a simple solution to this problem by providing a local reservoir of energy at the device, thus keeping supply impedance low. Bypass capacitors should be as close as possible to the LT1711/LT1712 supply pins. A good high frequency capacitor, such as a 1000pF ceramic, is recommended in parallel with larger capacitors, such as a 0.1F ceramic and a 4.7F tantalum in parallel. These bypass capacitors should be soldered to the output ground plane such that the return currents do not pass through the ground plane under the input circuitry. The common tie point for these two ground planes should be at the board ground connection. Such stargrounding and ground plane separation is extremely important for the proper operation of ultra high speed circuits. Poor trace routes and high source impedances are also common sources of problems. Keep trace lengths as short as possible and avoid running any output trace adjacent to an input trace to prevent unnecessary coupling. If output traces are longer than a few inches, provide proper
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termination impedances (typically 100 to 400) to eliminate any reflections that may occur. Also keep source impedances as low as possible, preferably much less than 1k. The input and output traces should also be isolated from one another. Power supply traces can be used to achieve this isolation as shown in Figure 1, a typical topside layout of the LT1712 on a multilayer PC board. Shown is the topside metal etch including traces, pin escape vias and the land pads for a GN16 LT1712 and its adjacent X7R 0805 bypass capacitors. The V +, V - and GND traces all shield the inputs from the outputs. Although the two V - pins are connected internally, they should be shorted together externally as well in order for both to function as shields. The same is true for the two V + pins. The two GND pins are not connected internally, but in most applications they are both connected directly to the ground plane.
171112 F01
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Figure 1. Typical LT1712 Topside Metal for Multilayer PCB Layout
Hysteresis
Another important technique to avoid oscillations is to provide positive feedback, also known as hysteresis, from the output to the input. Increased levels of hysteresis, however, reduce the sensitivity of the device to input voltage levels, so the amount of positive feedback should be tailored to particular system requirements. The LT1711/LT1712 are completely flexible regarding the application of hysteresis, due to rail-to-rail inputs and the complementary outputs. Specifically, feedback resistors can be connected from one of the outputs to its corresponding input without regard to common mode considerations. Figure 2 shows several configurations.
LT1711/LT1712
APPLICATIO S I FOR ATIO
Q VIN
+
LT1711 VIN
50
-
50k 50 Q V + = 5V V - = -5V VHYST = 5mV (ALL 3 CASES) VREF
Figure 2. Various Configurations for Introducing Hysteresis
TYPICAL APPLICATIO S
Simultaneous Full Duplex 75Mbaud Interface with Only Two Wires The circuit of Figure 3 shows a simple, fully bidirectional, differential 2-wire interface that gives good results to 75Mbaud, using the LT1712. Eye diagrams under conditions of unidirectional and bidirectional communication are shown in Figures 4 and 5. Although not as pristine as the unidirectional performance of Figure 4, the performance under simultaneous bidirectional operation is still excellent. Because the LT1712 input voltage range extends 100mV beyond both supply rails, the circuit works
750k 3V 4 14 RxD 3V
+ -
15
2
1/2 LE LT1712 13 16 3
1
750k 100k 3V 49.9 TxD 7 R2A 2.55k 11 R3A 124 R3B 124 R2B 2.55k ROA 140 R1B 499 R1A 499
+
5
49.9
8
1/2 LT1712 - LE 10 12 6 9
100k
Figure 3. 75Mbaud Full Duplex Interface on Two Wires
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50k Q 50 100k Q
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+
LT1711
VIN+ VIN- Q
+
LT1711
-
50
-
Q 100k
171112 F02
with a full 3V (one whole VS up or down) of ground potential difference. The circuit works well with the resistor values shown, but other sets of values can be used. The starting point is the characteristic impedance, ZO, of the twisted-pair cable. The input impedance of the resistive network should match the characteristic impedance and is given by:
RIN = 2 * RO *
R1||(R2 + R3) RO + 2 * [R1||(R2 + R3)]
750k
2
+ -
3
4 14 RxD
1
1/2 LT1712 LE 15 16 13
3V
3V R1C 499 ROB 140 6-FEET TWISTED PAIR ZO 120 DIODES: BAV99 x4 R1D 499 R2C 2.55k
750k 100k 3V 5 11 R3C 124 R3D 124 R2D 2.55k
+
7
49.9 TxD
1/2 LT1712 8 LE - 12 6 10 9
49.9
100k
171112 F03
9
LT1711/LT1712
TYPICAL APPLICATIO S
Figure 4. Performance of Figure 3's Circuit When Operated Unidirectionally. Eye is Wide Open
This comes out to 120 for the values shown. The Thevenin equivalent source voltage is given by:
VTH = VS *
(R2 + R3 - R1) (R2 + R3 + R1) RO * RO + 2 * [R1||(R2 + R3)]
FREQUENCY DEVIATION (kHz)
This amounts to an attenuation factor of 0.0978 with the values shown. (The actual voltage on the lines will be cut in half again due to the 120 ZO.) The reason this attenuation factor is important is that it is the key to deciding the ratio between the R2-R3 resistor divider in the receiver path. This divider allows the receiver to reject the large signal of the local transmitter and instead sense the attenuated signal of the remote transmitter. Note that in the above equations, R2 and R3 are not yet fully determined because they only appear as a sum. This allows the designer to now place an additional constraint on their values. The R2-R3 divide ratio should be set to equal half the attenuation factor mentioned above or: R3/R2 = 1/2 * 0.09761. Having already designed R2 + R3 to be 2.653k (by allocating input impedance across RO, R1 and R2 + R3 to get the requisite 120), R2 and R3 then become 2529 and 123.5 respectively. The nearest 1% value for R2 is 2.55k and that for R3 is 124. Voltage-Tunable Crystal Oscillator The front page application is a variant of a basic crystal oscillator that permits voltage tuning of the output frequency. Such voltage-controlled crystal oscillators (VCXO)
10
U
171112 F04
171112 F05
Figure 5. Performance When Operated Simultaneous Bidirectionally (Full Duplex). Crosstalk Appears as Noise. Eye is Slightly Shut But Performance is Still Excellent
are often employed where slight variation of a stable carrier is required. This example is specifically intended to provide a 4 x NTSC sub-carrier tunable oscillator suitable for phase locking. The LT1711 is set up as a crystal oscillator. The varactor diode is biased from the tuning input. The tuning network is arranged so a 0V to 5V drive provides a reasonably symmetric, broad tuning range around the 14.31818MHz center frequency. The indicated selected capacitor sets tuning bandwidth. It should be picked to complement loop response in phase locking applications. Figure 6 is a plot of tuning input voltage versus frequency deviation. Tuning deviation from the 4 x NTSC 14.31818MHz center frequency exceeds 240ppm for a 0V to 5V input.
1
Using the design value of R2 + R3 = 2.653k rather than the implementation value of 2.55k + 124 = 2.674k.
9 8 7 6 5 4 3 2 1 14.3140MHz 0 0 1 3 2 INPUT VOLTAGE (V) 4
171112 F06
14.3217MHz
14.31818MHz
5
Figure 6. Control Voltage vs Output Frequency for the Front Page Application Circuit. Tuning Deviation from Center Frequency Exceeds 240ppm
LT1711/LT1712
PACKAGE DESCRIPTIO U
Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 0.004* (3.00 0.102)
8
76
5
0.193 0.006 (4.90 0.15)
0.118 0.004** (3.00 0.102)
1 0.043 (1.10) MAX 0.007 (0.18) 0.021 0.006 (0.53 0.015) 0 - 6 TYP SEATING PLANE
23
4 0.034 (0.86) REF
0.009 - 0.015 (0.22 - 0.38)
0.0256 (0.65) BSC
0.005 0.002 (0.13 0.05)
MSOP (MS8) 1100
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
GN Package 16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 - 0.196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 0.009 (0.229) REF
0.229 - 0.244 (5.817 - 6.198)
0.150 - 0.157** (3.810 - 3.988)
1 0.015 0.004 x 45 (0.38 0.10) 0.007 - 0.0098 (0.178 - 0.249) 0.016 - 0.050 (0.406 - 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP 0.053 - 0.068 (1.351 - 1.727)
23
4
56
7
8 0.004 - 0.0098 (0.102 - 0.249)
0.008 - 0.012 (0.203 - 0.305)
0.0250 (0.635) BSC
GN16 (SSOP) 1098
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LT1711/LT1712
TYPICAL APPLICATIO
1MHz Series Resonant Crystal Oscillator with Square and Sinusoid Outputs Figure 7 shows a classic 1MHz series resonant crystal oscillator. At series resonance, the crystal is a low impedance and the positive feedback connection is what brings about oscillation at the series resonant frequency. The RC feedback around the other path ensures that the circuit does not find a stable DC operating point and refuse to oscillate. The comparator output is a 1MHz square wave (top trace of Figure 8) with jitter measured at better than 28psRMS on a 5V supply and 40psRMS on a 3V supply. At Pin 2 of the comparator, on the other side of the crystal, is a clean sine wave except for the presence of the small high
R10 1k R5 6.49k C5 100pF 1MHz AT-CUT R4 210 R1 1k R2 1k VS 2 R6 162 C3 100pF R7 15.8k C4 100pF
VS
+ -
1 7 LT1711 LE 5 6 SQUARE R9 2k VS R3 1k C2 0.1F 2
3
4
8
C1 0.1F
Figure 7. LT1711 Comparator is Configured as a Series Resonant Xtal Oscillator. LT1806 Op Amp is Configured in a Q = 5 Bandpass with fC = 1MHz
RELATED PARTS
PART NUMBER LT1016 LT1116 LT1394 LT1671 LT1713/LT1714 LT1719 LT1720/LT1721 DESCRIPTION UltraFast Precision Comparator 12ns Single Supply Ground Sensing Comparator 7ns, UltraFast Single Supply Comparator 60ns, Low Power, Single Supply Comparator Single/Dual 7ns, Low Power, 3V/5V/5V, R-R Comparator 4.5ns, Single Supply 3V/5V/5V Comparator Dual/Quad, 4.5ns, Single Supply Comparator COMMENTS Industry Standard 10ns Comparator Single Supply Version of the LT1016 6mA Single Supply Comparator 450A Single Supply Comparator 7ns/5mA versions of the LT1711/LT1712 4mA Comparator with Rail-to-Rail Outputs and Level Shifting Dual/Quad Version of the LT1719
171112f LT/TP 0401 4K * PRINTED IN USA
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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frequency glitch (middle trace of Figure 8). This glitch is caused by the fast edge of the comparator output feeding back through crystal capacitance. Amplitude stability of the sine wave is maintained by the fact that the sine wave is basically a filtered version of the square wave. Hence, the usual amplitude control loops associated with sinusoidal oscillators are not necessary.2 The sine wave is filtered and buffered by the fast, low noise LT1806 op amp. To remove the glitch, the LT1806 is configured as a bandpass filter with a Q of 5 and unity-gain center frequency of 1MHz, with its output shown as the bottom trace of Figure 8. Distortion was measured at - 70dBc and - 60dBc on the second and third harmonics, respectively.
2
Amplitude will be a linear function of comparator output swing, which is supply dependent and therefore adjustable. The important difference here is that any added amplitude stabilization or control loop will not be faced with the classical task of avoiding regions of nonoscillation versus clipping.
3V/DIV
VS
- +
7 6 1 4
171112 F07
1V/DIV
SINE
LT1806S8 3 R8 2k
1V/DIV
200ns/DIV
171112 F08
Figure 8. Oscillator Waveforms with VS = 3V. Top is Comparator Output. Middle is Xtal Feedback to Pin 2 at LT1711 (Note the Glitches). Bottom is Buffered, Inverted and Bandpass Filtered with a Q = 5 by LT1806
(c) LINEAR TECHNOLOGY CORPORATION 2001

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